发明名称 BIPOLAR INTEGRATED CIRCUIT
摘要 PURPOSE:To provide an accurate estimation for a performance of IC by a method wherein a monitoring bipolar transistor having an emitter layer with a width similar to a minimum width of emitter of the transistors in IC is arranged and its hFE is measured. CONSTITUTION:When an emitter layer of a bipolar transistor is made under a dispersion from a doped poly-Si, hFE is decreased as its width is decreased if the emitter width is less than 5mum. Then, if a monitoring bipolar transistor having an emitter layer with its width similar to a minimum emitter width of the transistor formed in IC is provided to measure its hFE, a lower limit value of hFE of the bipolar transistor in IC may be assured, a performance of IC may accurately be evaluated.
申请公布号 JPS56134763(A) 申请公布日期 1981.10.21
申请号 JP19800038670 申请日期 1980.03.26
申请人 CHO LSI GIJUTSU KENKYU KUMIAI 发明人 SHINOZAKI SATOSHI
分类号 H01L21/66;H01L21/331;H01L29/08;H01L29/73 主分类号 H01L21/66
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