| 摘要 |
PURPOSE:To execute processing at a high speed, by making sequence relation of binary numerical values which has been classified into three correspond to each internal status, and changing the order of input signals in accordance with the sequence relation signified by each internal status to output them. CONSTITUTION:When the reset signal R becomes ''0'', all the status signals Y1-Y12 of outputs of the driving circuit and the memory circuits 30-1-30-6 become ''0''. These status signals are input to the NOR gate 40 and the status signal YO of its output becomes ''1''. As a result, the initial status is set, and subsequently, the operation is started as R=1. The circuit 30-1 detects the combination of the input signals X1-X3 when the signal Y0 is ''1'', and makes the signal Y1 ''1''. When the signal Y1 becomes ''1'', the signal Y0 becomes ''0'', and transition of the status from the initial status occurs. Also, in this case, the signal Y7 is made ''1''. Moreover, the combination of the input signals X1, X2 is detected in the same way, then the signal Y1 is made ''0'', and also the signal Y12 is made ''1''. In this way, transition of the status is executed exactly. The output circuit changes the orde of three input signals in accordance with the sequence relation by said classification to outputs them to the three output signal lines. |
