| 摘要 |
PURPOSE:To obtain a delay time adjusting circuit which is inexpensive and can be changed to a monolithic IC, removing a defect of the delay circuit using a delay line, by constituting the delay circuit of cascade connection of the element to be used for the logical circuit. CONSTITUTION:A signal which has been input to the input terminal 60 of the delay circuit 10 is delayed by the gate circuits 101-103 by 3 stage portion of gate, and after that, it is output as a delay signal to the output terminal 70 through the selecting circuit 20. In this case, when the combination of the logical level ''0'' or ''1'' provided to the control terminals 80, 90 is changed suitably, a signal which is output to the output terminal 70 can be adjusted in terms of time at the delay time interval of 1 stage portion of gate at least. In this regard, in the delay circuit, the gate circuit 105 is used for equalizing the propagation delay time in each gate circuit by making the load same as that of the gate circuits 101-104 connected to the selecting circuit 20, and it can be omitted in case when the fluctuating load of the propagation delay time can be disregarded. |
