| 摘要 |
<p>PURPOSE:To absorb the jitter of + or -1 bit, by storing both the write and read clocks of data and reading the data by the output obtained when a coincidence is secured between the write and read outputs. CONSTITUTION:The write clock W CLK is supplied to the terminal S of the FFF4 to generate an output through the output terminal Q of the FFF4. This output is supplied to the AND circuit G. The read clock R CLK is supplied to the terminal S of the RSFFF5, and an output is generated through the terminal Q of the FFF5 to be supplied to the circuit G. The pulse P1 is delivered from the circuit G and supplied to the terminal C of the DFFF2. An output is delivered through the terminal Q of the FFF2 and supplied to the terminal D of the DFFF3 to be delivered as the DATA OUT by the R CLK.</p> |
