发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To make the synchronous memory operation independently of the types of memory elements, by providing the counter managing the busy condition of the main memory device and selecting arbitrarily the value of the counter. CONSTITUTION:An input/output device 2 and a main memory unit 3 are connected to a central processing unit 1, and the central processing unit 1 is provided with an instruction control section 4 and a memory control section 5. The main memory unit 3 is sectioned into a plurality of banks, and a memory control section 5 is provided with the means designating the usage inhibiting period of each bank and the counter operated during the use of bank, and each bank of the main memory unit 3 can be in synchronous operation, by selecting the period of the said usage inhibition from the counter value and resetting the usage.
申请公布号 JPS56101257(A) 申请公布日期 1981.08.13
申请号 JP19800002889 申请日期 1980.01.14
申请人 HITACHI LTD 发明人 SHIMIZU TSUGUO;MATSUURA TSUGUO;TORII SHIYUNICHI
分类号 G06F12/06;G06F12/00;G06F13/42 主分类号 G06F12/06
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