| 摘要 |
PURPOSE:To prevent latch-up by providing an n<+> type region between the regions of source, drain and channel and a semiconductor substrate for a P-channel-type MIS transistor and a p<+> type region for an N-channel-type MIS transistor in a similar position, respectively. CONSTITUTION:On an n<+> type Si substrate 1 are formed diffusely an n<+> type layer 2 and a p<+> type layer 3, being separated by the 1st insulating separation layer 4, and the side of the layer 2 is used for the P-channel-type MIS transistor and the side of the layer 3 for the N-channel-type MIS transistor. In this way, the n<+> type layer 2 is positioned as an underlay of the P-channel-type element and the p<+> type layer 3 as that of the N-channel-type element. And, an n<-> type layer 5 to be channel is made to grow on the layer 2, at both ends thereof the p<+> type source region and the drain regions 11 and 12 are provided, and between source and drain regions a gate electrode 9 is provided through the intermediary of a gate insulation film 8. Next, element regions of quite the same structure are also formed on the layer 3 and a gate electrode 10 is fitted thereto. In this way, a carrier caused by alpha rays and the like is eliminated in a short time. |
