| 摘要 |
PURPOSE:To improve the processing speed, by omitting post normalization of addition and subtraction results on a basis of the output of the unnecessity deciding decoder which indicates that post normalization is unnecessary and by obtaining the final result in a normalized form. CONSTITUTION:Contents of exponential part EXP of the first operand register 1 and contents of exponential part EXP of the second operand register 2 are operated by exponential part upper bit subtracting circuit 3, exponential part lower bit adding and subtracting circuit 4, and mantissa start digit subtracting circuit 5. The operated result is applied to shifters 8 and 9 through decoder 6 for comparison of exponential parts, and contents of mantissa are matched to each other for digit, and addition and subtraction are performed by carry propagation adder 10. The output of decoder 6 is applied to post normalization unnecessity deciding decoder 7, and signal ANSOK indicating that post normalization is unnecessary is reported to the microprogram by decoder 7, thus omitting post normalization of the addition and subtraction result. |
