发明名称 MULTIPLEEVALUED LEVEL OUTPUT CIRCUIT
摘要 PURPOSE:To prevent a latch-up state and the destruction of an element by mutually connecting output terminals of a couple of inverters differing in power voltage and by turning on and off those inverters through complementary switching. CONSTITUTION:As the 1st control signal is helt at level [L], inverters composed of MOS transistors T1 and T2 are turned on to generate outputs of levels VDD1 and VSS1 obtained by inverting the input. When the 1st control signal is held at level [H], MOS transistors T1 and T2 are turned off regardless of the input and the inverter outputs are in high impedance state. In response to the 2nd control signal, the same operation is performed to hold outputs of MOS transistors T3 and T4 at VDD2 and VSS2. The 1st and 2nd control signals are both inhibited from being at level [L].
申请公布号 JPS5691536(A) 申请公布日期 1981.07.24
申请号 JP19790169756 申请日期 1979.12.26
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 YUYAMA TOSHIO;SHIRAKI RIYUUZOU;WATANABE SEIJI
分类号 H03K19/20;H03K19/094 主分类号 H03K19/20
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