| 摘要 |
PURPOSE:To allow the memory cell array circuit driven by three basis levels of different polarities to be a monolithic IC together with the driving circuit by employing IGFETs whose channel conductivity types are inverse to each other to generate driving signals of different polarities. CONSTITUTION:On a P type silicon substrate 10, an N<+> type source region 11, an N<+> type drain region 12, an N type channel region 13, a gate insulating film 14 and gate elctrodes 15 and 16 are formed to constitute a memory cell. An X decorder driver 21 to generate a driving signal VR for read-out and a Y decorder driver 22 to convert the address input signal into a driving signal VG1 for erasing are constituted by the N channel IGFET, and a Z decorder driver 23 to convert the address input into a writing signal VG2 of the different polarity by the P channel IGFET. Said constitution permits the driving circuit of three basis levels having different polarities to readily be a monolithic IC together with the memory cell. |
