| 摘要 |
PURPOSE:To connect two inverter stages in series in a small area by a method wherein a gate electrode is installed on a P type Si layer on an insulating substrate through a mediation of an insulating film and a P layer and an n layer are installed at its both sides. CONSTITUTION:An Si 32 is grown on a sapphire 30 and after an approximately half of its thickness is etched at an end part thereof, an oxide film 34 is formed to produce a flat surface. B is injected into the Si 32 to form a P layer and a P<+> layers, D2, S2 by injecting B using a resist mask. Next thereto, a gate oxide film 36 is installed and a gate electrode G is attached thereto, and As is injected to form an n layers D1, S1. An S1-G-D1 and an S2-G-D2 constitute an enhancement type FET and a depletion type embedded channel FET, respectively. When D1 is connected to a power source VCC, D2 is connected to the earth, G is connected to an input terminal, and S1, S2 are jointly connected to an output terminal, then, an equivalent to a series connection of two inverter stages is formed and a circuit occupation area can be reduced to approximately 1 piece of a FET area. |
