| 摘要 |
PURPOSE:To obtain the pulse-width-modulated signal of digital data, by generating a pulse that rises when bits of the data all disagree with those of a counter counting continuously and falls when all bits agree. CONSTITUTION:Input signal 6 is operated as prescribed by arithmetic part 5 under the control of outputs 4a-4f of counter 3 and when the contents of counter 3 are all ''0'', they are inputted to latches 8a-8e. When outputs 4a-4f of counter 3 all disagree with outputs 9a-9e of latches 8a-8e and 3f is at ''1'', output 16 is at ''0'', setting flip-flop 20. On the other hand, when both outputs agree completely and 3f is at ''0'', output 15 is at ''0'', resetting flip-flop 20. Output 23 varies in pulse width the contents of latches 8a-8e. |
