| 摘要 |
A synchronous motor is driven by applying cyclical or digital data through a phase locked loop whose loop filter integrates with a time constant equal to or greater than the inertial delay of the motor from start to its operating speed. According to one embodiment, the frequency output of the phase locked loop is further controlled with a digital rate multiplier whose phase effects are minimized by operating the VCO at a multiple of the input frequency and feeding the VCO voltage back through a frequency divider. According to another embodiment, the frequency control is obtained with a preliminary phase locked loop with a normal filter but a high frequency VCO whose feedback is divided by a value n, and then dividing the output of the main loop by m. Suitable counters may be used to stop and start the drive.
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