发明名称 VERTICAL INSULATED-GATE FIELD-EFFECT TRANSISTOR
摘要 PURPOSE:To shorter reverse recovery time of a diode present between source and drain, by setting resistivity of an epitaxial layer to be M times (M>1) as large as resistivity determined by relation between resistivity and dielectric strength observed when extension of a depletion layer is ensured, and decreasing the thickness of the epitaxial layer corresponding thereto. CONSTITUTION:An N-type layer 2a is epitaxially grown on a highly doped N-type semiconductor substrate 1. A P-type diffused layer 3 is formed on a predetermined region on the layer 2a and, further, a highly doped N-type dif fused layer 4 is formed in a predetermined region on the layer 3. A gate elec trode G, a source electrode S and a drain electrode D are formed on predeter mined regions on the N-type expitaxial layer 2a, the P-type diffused layer 3 and the N-type diffused layer 4. Resistivity Pepi of the N-type epitaxial layer 2a is set to be twice (M=2) as large as resistivity Pepi determined by relation between dielectric strength and resistivity Pepi of the epitaxial layer as observed when extension of a depletion layer is ensured (preferably M>=1.5). In this man ner, a diode between the source and the drain is allowed to have shortened reverse recovery time without changing dielectric strength or ON resistance.
申请公布号 JPS6457757(A) 申请公布日期 1989.03.06
申请号 JP19870216119 申请日期 1987.08.28
申请人 NEC CORP 发明人 YANAGAWA HIROSHI
分类号 H01L29/78 主分类号 H01L29/78
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