| 摘要 |
PURPOSE:To obtain a CMOS buffer circuit whose DC current is small even when load capacity is large, by using a logic method consisting of two inverters and an NOR gate and a different-channel MIS transistor. CONSTITUTION:Input terminal A is connected to inverter I11, output terminal B of inverter I11 to the input terminal of inverter I12, output terminal C and input terminal A of inverter I12 to the input terminal of NOR gate R11, output terminal B of inverter I11 to the gate terminal of p channel MIS transistor P11, and output terminal D of NOR gate R11 to the gate terminal of n channel MIS transistor N11. Further, source terminals of MIS transistors P11 and N11 are connected to electric power sources VCC and VSS respectively. Furthermore, drain terminals of MIS transistors P11 and N11 are connected in common to output terminal OUT. Thus, the CMOS buffer circuit can be obtained which has small DC current even when load capacity is large. |
