发明名称 VARIABLE CLOCK FREQUENCY COMPUTER
摘要 <p>PURPOSE:To make it possible to execute continuous instructions by avoiding waste of time, by performing the operation by the clock frequency which is suitable for each execution cycle. CONSTITUTION:A digital signal 8 according to the execution time is output to the D/A conversion circuit 5 from the decoding circuit 4, corresponding to classfication of the instruction 7 which is output from the control circuit 1. An optimal clock pulse 9 to the execution cycle based on the above digital signal is generated in the V/F conversion circuit 6, and it is provided to both the control circuit 1 and the operation circuit 2. Thus, waste of the execution time can be avoided by means of execution of the clock frequency which is optimal to each execution cycle.</p>
申请公布号 JPS5647843(A) 申请公布日期 1981.04.30
申请号 JP19790123386 申请日期 1979.09.25
申请人 MITSUBISHI ELECTRIC CORP 发明人 KISHIMOTO KAZUO
分类号 G06F9/30;G06F1/04;G06F1/08 主分类号 G06F9/30
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