发明名称 LOGIC CIRCUIT USING SCHOTTKY OR PPN JUNCTION GATE TYPE FIELD EFFECT TRANSISTOR
摘要 PURPOSE:To increase the amplitude of logic, by connecting a diode to the gate of the 1st and 2nd FET transistors having the inverter function, in which the source is grounded and the drain is connected to the power supply via a load. CONSTITUTION:In FETs Q1, Q2, the source is grounded, the drain is connected to the power supply E via loads R1, R2, diodes Z', Z are respectively connected to the gate in forward direction, and biase resistors R', R are connected between the gate and ground. When the signal X1 of logic 1 is input to the terminal T1, the signal X2 of logic 0 is output at the drain of FETQ1 and the signal X3 of logic 1 is output at the drain of FETQ2, and when the signal X1 is at logic 0, the signals X2, X3 are respectively at logic 1, 0, showing the inverter function. By connecting the diode to the gate of each FET, the level of logic 1 can be increased to the voltage which is the sum of the gate diffusion voltage of FET and the drop voltage of the diode, enabling to increase the amplitude of logic. Further, by inserting the baias resistance to the gate, the logic conversion speed can be increased.
申请公布号 JPS5646340(A) 申请公布日期 1981.04.27
申请号 JP19790122198 申请日期 1979.09.22
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 OOMORI MASAMICHI;NAGAFUNE KAZUO
分类号 H03K19/08;H03K19/0952;(IPC1-7):03K19/094 主分类号 H03K19/08
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