| 摘要 |
PURPOSE:To make operations high-precision and high-speed, by changing the clock period of a shift register to control the conversion precision. CONSTITUTION:The analogue signal at input terminal 8 is sampled by sample hold circuit 1, and the sampled value is held only during a fixed time for conversion to a digital signal. The hold signal is sent to comparator 3. Meanwhile, shift register 5 generates shift pulses to drive DA converter 2. The output of AD converter 2 and the output of sample hold circuit 1 are compared with each other successively by comparator 3 and are encoded. In this case, the analogue signal is converted up to a prescribed number of bits in a speed higher than that for conversion of succeeding bits, and is converted for bits following the prescribed number of bits by delaying the period of clocks. |
