| 摘要 |
PURPOSE:To easily set, change and analyze the test data by storing this data into a 1st memory device for each block and at the same time storing the processing result of the test data into a 2nd memory device for each block. CONSTITUTION:The test data for simulation is written into each address of a ROM 2 every byte and the test data on the ROM 2 is successively outputted every byte for the address designated by the output of a counter 1 for basic clocks CLK. The output test data is converted into the serial data SD by a parallel/serial converter 3 and processed by a digital signal processing circuit 4. Then the output data SDD of the circuit 4 is converted into the parallel data by a serial/parallel converter 6 and stored every byte in a RAM 7 of the address designated by the output of a counter 5 which counts the clock signals CP2 outputted from the circuit 4. |
