| 摘要 |
A circuit comprising a signal generating circuit and an interrupt enable circuit. The signal generating circuit has an input connected to receive a trigger signal and an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuit is responsive to the trigger signal for initiating the timing cycle. The interrupt enable circuit is connected to the signal generating circuit for interrupting the timing cycle in timed relation to an interrupt signal and for reinitiating the timing cycle in timed relation to a reset signal, the interrupt enable circuit being connected to receive the interrupt and reset signals. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.
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