| 摘要 |
PURPOSE:To attain stable operation without causing malfunction up to an extremely high frequency by using a one-phase pulse signal for the operation of a shift register. CONSTITUTION:Between positive potential VDD and reference potential GND, P channel MOSFETs 11 and 12 and N channel MOSFETs 13 and 14 are interposed in series and the connection point between FETs 12 and 13 is used as output terminal 15; and P channel MOSFETs 16 and 17 and N channel MOSFET18 are connected in series and the connection point between FETs 17 and 18 is used as output terminal 19. Then, FETs 12 and 13 are supplied with input signal IN at gates, signal A at output terminal 15 is supplied to the gate of FET17 and outputted by way of inverter 20, and signal B at output terminal 19 is supplied to the gate of FET11. Further, respective gates of FETs 14, 16 and 18 are supplied with one-phase pulse signal phi and when signal IN varies synchronizing with the fall of phi, signal OUT varies synchronizing with the rise of phi a half bit delayed behind phi. |
