发明名称 |
Process for producing an integrated multi-layer insulator memory cell |
摘要 |
An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.
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申请公布号 |
US4257832(A) |
申请公布日期 |
1981.03.24 |
申请号 |
US19790058555 |
申请日期 |
1979.07.18 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
SCHWABE, ULRICH;JACOBS, ERWIN |
分类号 |
H01L27/112;H01L21/033;H01L21/28;H01L21/822;H01L21/8246;H01L21/8247;H01L27/06;H01L27/088;H01L27/10;H01L29/51;H01L29/788;H01L29/792;(IPC1-7):H01L21/22 |
主分类号 |
H01L27/112 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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