| 摘要 |
PURPOSE:To obtain the address buffer circuit which simplifies the memory system, by performing required operation at active and nonactive with a single clock. CONSTITUTION:When the clock input phi is ON at the state that the address signal is input from the terminal A, the transistor Q25 is condictive and the power supply and the reference postential VDD, VSS1 are bypassed to operate the inverter chain of transistors Q21-Q24. Simultaneously, FSFF consisting of transistors Q28-Q33 is operated via the switching transistors Q26, Q27, and the output terminal A' of the push-pull inverter of the transistors Q34-Q37 and the opposing output terminal are respectively at high and low level for static operation and specified signal is picked up at the decoder side. On the other hand, when the clock phi is OFF, similarly RSFF is at reset operation, both the output terminals are at high level of potential VDD, the decoder output is at low level, power consumption is substantially zero, and the memory system can be simplified. |
