发明名称 COMPENSATED INPUT CIRCUIT FOR USE WITH BIPOLAR RETURN TO ZERO LINE SIGNALS
摘要 An input circuit for use with bipolar RT2 signals is transformer coupled for d.c. isolation and line impedance matching. Part of the input signal BL1 is tapped off, rectified and smoothed to provide a d.c. voltage which follows the amplitude changes of the input line signal. The d.c. voltage is used to vary the threshold of a level detector circuit which comprises a long tail triplet (TR1, TR2, TR3). Transistors TR1 and TR2 provide the signal output conditions whereas TR3 provides the variable threshold. The signals amplified by TR1 and TR2 are further amplified by transistors TR4 and TR5 which provide, at their collectors, the respective positive and negative mark binary output signals. <IMAGE>
申请公布号 ZA8000491(B) 申请公布日期 1981.01.28
申请号 ZA19800000491 申请日期 1980.01.28
申请人 PLESSEY CO LTD 发明人 WATTEN L;SMITH R
分类号 G11B20/14;H03K5/02;H04L25/06 主分类号 G11B20/14
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