Direct memory access control device

摘要

In a computer wherein a central processor and at least one peripheral controller have access to a memory, this latter is divided into two simultaneously accessible zones, namely a private zone accessible by the processor and a direct access zone accessible both by the processor and by the peripheral controller. A logic unit synchronizes the controller's access to the direct access zone with the processor's access to the private zone, the controller's access being delayed, if necessary to occur simultaneously with the processor's access. The peripheral controller's access is thereby achieved without interruption of processor operations.