| 摘要 |
PURPOSE:To secure the easy detection for the correct or erroneous reception data of N-byte, by deciding error through the comparison between the head one byte and the last one byte of the shift register and then carrying out this error decision in sequence once and every N+1 bits. CONSTITUTION:The data of N-byte are supplied in sequence to 1-byte shift register 7 of N+1 byte shift register 15 from the input end of the serial input data and by the shift clock, and then to N-1 byte shift register 8 and register 7. Then the inverse data of N-byte in which the bit of each byte is inverted are supplied in sequence and by one byte to register 7. Thus the head one byte enters 1-byte shift register 9 when the inverse data of the first one byte enters register 7. Thus the error decision 10 is given to one byte of registers 7 and 9 each. If this decision result is correct, the output of circuit 10 is sent to N-byte latch 14. And the error decision of N-1 times is carried out in sequence and every time N+1 bytes enter. Thus the detection can be given easily to the error for the N-byte reception data. |
