| 摘要 |
PURPOSE:To avoid the DC component in the modulation signal, by obtaining binary balance code through the conversion of binary input data into four data of a given pattern according to their relations before and after. CONSTITUTION:For example, the binary input data 164 is fed to the address signal forming unit 83 via the terminal 82, and the address signal is formed at the forming unit 83 with the data from the data separator 85 and the input data and it is fed to the memory 84. The data of the address designated with the address signal is picked up from the memory 84 and fed to the separator 85, where the data are separated into those for address signal and for output, and the latter becomes the serial data at the parallel/serial converter 86 and is fed as the modulated signal 166 from the terminal 88. To allow the input data to invert the level at the boundary point of bit cell, and at the points of 1/4, 1/2 and 3/4 of the bit cell, the data is converted into four patterns, binary balanced code, no DC component is included, and the level inverting interval is 1.25 times or more and 2.5 times or less in comparison with the bit cell interval 171. |
