发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To make the multi-processor constitution of various numbers of processors possible with a high cost performance by connecting plural CPUs into a ring through connection means. CONSTITUTION:When store request occurs in CPU0, the request address is given to main memory MS to perform write. If data of the address has been taken into buffer memory BS11, write to BS11 is performed. Then, the address and the CPU number are outputted as cancel request from output end O. Output end O of each CPU is connected to input end I of one of adjuacent CPUs by connection line L, and cancel request is transferred to CPU1 and is further transferred to CPU2 and CPU3, and the same operation as the cancel operation in CPU0 is performed. When the address and the CPU number of cancel request from CPU3 are inputted to input end I of CPU0, they are given to cancel buffer 36, and the address is made invalid if an address agreeing with the address is held in buffer 36.
申请公布号 JPS55134459(A) 申请公布日期 1980.10.20
申请号 JP19790041118 申请日期 1979.04.06
申请人 HITACHI LTD 发明人 MATSUURA TSUGUO;TORII SHIYUNICHI;SHIMIZU TSUGUO
分类号 G06F12/08;G06F15/16;G06F15/173 主分类号 G06F12/08
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