Electronic delay line for analogue signal - uses bucket brigade circuit with input circuit providing sampled voltage held constant for duration of charge transfer clock signals

摘要

The delay line has the charges representing the values of the sampled analogue input transferreed through the odd and even storage chains via respective clock signals (T1, T2) of identical frequency and amplitude, but offset by 180 degrees. Each storage chain element comprises a transistor with a charge capacitor coupled to its control electrode, the first and last chain elements respectively associated with an input and an output circuit. The input circuit (Q1..Q9) has an output (A) providing an undelayed sampled version of the analogue input and it is supplied with two further clock signals (T3, T4) causing the output voltage to be held constant for the duration of the two clock signals (T1, T2) controlling charge transfer.