| 摘要 |
<p>PURPOSE:To quicken read operation by reducing the number of stages by using one transfer gate MISFET in common for two selecting operations. CONSTITUTION:Transfer gate MISFETs Q1 and Q2, and Q1' and Q2' which select bit lines of memory matrix parts 1a and 1b are provided and controlled in common by Y address decoder 3. On sides of read circuit 4 and write circuit 5, transfer gate MISFETs Q3 and Q4, and Q3' and Q4' are provided respectively. Then, respective FETs Q3 and Q4, and Q3' and Q4' are controlled by the output of AND between address signal A10 selecting memory part 1a or 1b, and write signal R. Thus, the number of stages of series transfer gates MISFET can be reduced to two, and the resistance and parasitic capacity of read signal lines, therefore, decrease, so that a read speed can be increased.</p> |
