发明名称 ERROR RECOVERY SYSTEM OF LOGIC UNIT
摘要 PURPOSE:To recover completely an error when a fixed fault occurs to CPU by stopping execution on detecting the error by several logic units, by displaying whether an error occurrence instruction is allowed to be reexecuted or not, and then by restarting the execution by a recovery controller when it is allowed. CONSTITUTION:The moment error detection circuit 130 detects an error, clock oscillation circuit 131 is stopped and at the same time, a job in process is interrupted by control part 31 of recovery controller 30 to start control over a recovery process, so that the contents of program operatable register groups 111-119 of CPU10 will be read in via stand-by interface 121. In unit 30, instruction retry disability indicator 132 judges whether an instruction at the time of the occurrence of the error can be retried or not. When it can be retried, it is retried by a signal from unit 30 and when not, a job in process is interrupted by CPU20 to execute an error instruction.
申请公布号 JPS5587251(A) 申请公布日期 1980.07.01
申请号 JP19780162429 申请日期 1978.12.26
申请人 NIPPON ELECTRIC CO 发明人 FUJIWARA TSUNETAKA
分类号 G06F11/14;G06F11/00;G06F11/18 主分类号 G06F11/14
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