| 摘要 |
PURPOSE:To enhance high-frequency characteristic by interposing n-layer in the FET areas of p<->-type and n<-->-type channels to prevent punch-through and latch-up generation. CONSTITUTION:As ions are injected into a p<->-type Si substrate 1a to form n-layer 12 which is overlaid with an addition-free n<--> epitaxial layer 13, and the layers 13, 12 are anisotropically etched. Then, the substrate 1a is overlaid at the specified locations with SiO2 film 16a, Si3N4 film 17a, The layer 13 also selectively overlaid with SiO2 film 16b and Si3N4 film 17b. Using mask of resist 18, p-type invertion-prevention layer 14 is formed. Thereafter, oxide film 7 is formed by heat treatment, then the SiO2 film and Si3N4 film are etched away. On each of new gate oxide film 5a, and 5b, n-type polycrystalline silicon gate layers 6a, 6b, and resist films 19a, 19b are formed which is followed by B ion injection to form p<+>-layers 4a, 4b, and p- layers 20a, 20b. Using resist mask 21, P ion is injected to transform the layers 20a, 20b to n<+>- layers 3a, 3b. Then, general procedures follow to provide a CMOS device having a very good operation properties. |
