发明名称 TIME SWITCH CONTROL SYSTEM
摘要 PURPOSE:To realize an economical constitution and high-speed operation for reading the information by dividing the time switch memory of the time-division exchange into several blocks and then applying the address signals of the memory to the selection circuit and each memory element at one time. CONSTITUTION:The time switch memory of the time-division exchange is formed with several units of blocks, and part of the memory address signals is applied to selection circuit SEL. The rest address signals are applied simultaneously to memory elements M0-Mn, and the information read simultaneously out from elements M0-Mn are selected through circuit SEL and then delivered. As a result, the decoder to give the selective action to each memory element can be omitted, and at the same time the reading information of each memory element is delivered via circuit SEL not the wired OR. Thus the rounding of the waveform is reduced to decrease the dispersion of the output time, realizing a high-speed action.
申请公布号 JPS5573193(A) 申请公布日期 1980.06.02
申请号 JP19780146251 申请日期 1978.11.27
申请人 FUJITSU LTD;NIPPON TELEGRAPH & TELEPHONE;OKI ELECTRIC IND CO LTD;NIPPON ELECTRIC CO;HITACHI LTD 发明人 KATSUYAMA TSUNEO;HIRAI ATSUSHI;OOWADA SHIYUUZOU;MATSUMOTO TAKASHI;WATANABE NOBORU
分类号 H04Q3/52;H04Q11/04 主分类号 H04Q3/52
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