Fieldistor-Tetrode

摘要

1,071,976. Semi-conductor devices. HUGHES AIRCRAFT CO.. March 10, 1966 [March 23, 1965], No. 10564/66. Heading H1K. A twin gate, multi-channel F.E.T. comprises two grid-like gate regions each surrounded by a guard region, the purpose of which is to limit the current path to the regions containing the gate electrodes. As shown, Fig. 1, the device is produced by vapour depositing an N-type silicon layer 4 on an N+ type substrate 2, diffusing-in two grid-like P-type gate regions 6, 61 using an oxide masking technique, epitaxially depositing a further layer of N-type silicon over the gate regions, diffusing- in boron to form P+ type guard rings 10, 101 surrounding gate regions 6, 61 respectively, diffusing-in arsenic to form N+ type source and drain regions 8, 81, and diffusing or alloying regions 12, 121 to provide connections to gate electrodes 6, 61. The first deposition step may be replaced by diffusing an N+ type region 2 into an N-type wafer 4, and source and drain regions 8, 81 may also be produced by alloying antimony-containing gold to the surface and the alloying depth may be restricted by using a layered gold-silver-gold structure. Gold layers (16, 18, 20) are vapour deposited over the oxide layer (14), to provide electrodes and metallic " bumps " (22, 26, 24) are provided on them, Fig. 2 (not shown), for orientation and circuit connection when the device is encapsulated by applying glass over the upper surface and fusing to form layer (28), Fig. 8 (not shown). The two guard rings (10, 101) may be combined into a single figure-of-eight structure, Figs. 3 and 4 (not shown). Although separate contacts may be applied to the gate electrodes the device illustrated has gate (61) connected by gold layer (20) to the source (8) to reduce the feedback capacitance between drain and control gate. This arrangement is said to be equivalent to two single gate F.E.T.'s connected in series with appropriate gate connections. Fig. 6 (not shown). An " in-line " device, Fig. 5 (not shown), may be produced by diffusing-in gate region (61), epitaxially depositing an N-type layer, diffusing- in gate region (6) above region (61), epitaxially depositing an N-type layer, diffusing-in a single guard ring (10) surrounding both gates, providing source region (8), and making connections (12, 121) to gates (6, 61) respectively. Connection (12) may be partially formed and then completed simultaneously with the formation of connection (12). The semi-conductor material may also be germanium or an A III B v compound such as aluminium phosphide, aluminium arsenide, aluminium antimonide, gallium phosphide, gallium arsenide or indium phosphide.