| 摘要 |
<p>A method and an apparatus for phase synchronization in a synchronous data transmission system, which transmits a binary pulse train from a transmitter to a receiver by means of an amplitude-modulated carrier. The modulation is of the so-called single-side band type (SSBAM) and the modulating signal which has been derived from the input data flow consists of superimposed pulses of so-called Partial-Response Class 4 type. The receiver clock generator consists of a digital phase-locked loop (TK, FD) controlled by level crossovers in the base-band signal, in which there is arranged between the phase detector (FD) and the oscillator (TK) a sorting circuit (SD), which sorts out and passes through to the oscillator (TK) only such information related to detected level crossovers of a predetermined first category. Further, carrier regeneration is provided by a second phase-locked loop (CR) in series with a phase correction circuit (FK). The phase correction is initiated from the sorting circuit (SD) for level crossovers of a predetermined second category. </p> |
