| 摘要 |
<p>PURPOSE:To switch clocks without stopping a data processing unit by switching them at a time when the phase relation between the current clock and another clock becomes optimum. CONSTITUTION:In case of the frequency of clock A higher than that of clock B, when a request to switch clock B to clock A or switch clock B to clock A is issued, the request is transferred to the data input of FF26 through OR gate 25, and AND between the output of FF26 and the inversion signal of OR gate 24 is operated by AND gate 28 when the output of OR gate 24 is ''0'', and timer 29 is triggered by this signal. The output of timer 29 becomes ''1'' and is broken to ''0'' after a fixed time. At this break time, the output of inverter 30 triggers FF31. In case that FF31 is set to ''0'', clock B is taken in by AND gate 34 and is outputted as clock C through OR gate 35. The power settlement signal of the processing unit can be used as the clock switching request.</p> |
