| 摘要 |
PURPOSE:To realize a large capacity and a high speed for the memory and thus to decrease the power consumption at the nonselection time by securing the paired MOS transistor's circuit constituting the gate circuit and with different amounts of floating capacity secured for each of the paired circuits. CONSTITUTION:When enhancement-type field effect transistors Q5-Q7 are conducting among these transistors plus load field effect transistors Q3 and Q4, both points (b) and (c) are at the earth potential. With cut-off of Q7, C3 among floating capacities C2 and C3 contains the gate input of the next step, thus obtaining the relation of C2<<C3. As a result, point (c) reaches the fixed level earlier than point (b) to accelerate the resistance reduction of Q4 as well as to accelerate the precharge of point (b). In case Q7 is on, the discharge is also accelerated for point (b). While with application of the earth potential to the gates of Q5 and Q6 at the nonselection time, the discharge is eliminated at points (b) and (c), thus decreasing the power consumption. |
