| 摘要 |
PURPOSE:To reduce the number of wires for carry and the number of FET's, by forming the carry signal delivery line in the series connection of transfer gates which are conductive when the output signal of each digit except the most significant bit of the binary count value is at logical value 1. CONSTITUTION:When the output signal 1a in one digit is at logical value 1, the transfer gate 1g of half carry is conducted, and when the clock signal beta is at high level, the carry signal of the logic value 1 is fed to the second digit. The second digit inverts and makes the output signal 2a as the logic 1 only when the signal 1a is at 1 and every time when the clock signal a is at logical value 1. When the signals 1a and 2a are both logical 1, the gates 1g and 2g are conducted and the carry signal is fed to the next digit when the signal beta is at high level. Similarly, the operation is made to the n digit 4 to perform binary counter operation. Thus, the number of carry Tr and the number of wires can remarkably be reduced. |
