发明名称 LOGIC CIRCUIT
摘要 <p>PURPOSE:To speed up the operation speed with a simple constitution, by building block for a plurality of MOSFET's and operating only the selected block. CONSTITUTION:A plurality of blocks 3011 to 3044 are provided by taking the block selection MOSFETQ1 and the memory cell MOSFETQ2 to Q5 as blocks, and each one end of blocks is commonly connected 321 to 324, 35 and the common connection is connected to the load element 36. Further, either one of the gate electrodes of FETQ1 of each block is selected and connected 331 to 334 to the cell selection decoder 34 to supply drive signal, and the gate electrodes of FETQ2 to Q5 corresponding between blocks are commonly connected 371 to 374. Further, those common connections are connected to the block selection decoder 38 and the column selection decoder 39 which supply the drive signal except selected connection. Thus, the operation speed can be quickened with a simple constitution.</p>
申请公布号 JPS5523604(A) 申请公布日期 1980.02.20
申请号 JP19780076286 申请日期 1978.06.23
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 NAGATSUNE AKIRA
分类号 G11C17/00;G11C17/12;H03K19/017;H03K19/0944;H03K19/173;H03K19/177 主分类号 G11C17/00
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