| 摘要 |
<p>An electronic timepiece includes a first memory adapted to time count data in address positions in such an order that a larger time unit is positioned ahead of a smaller time count unit, and a second memory adapted to have address positions designated in a manner to correspond to the address position of the first memory and store carry requirement numerical data, each corresponding to a final time count value of the respective time count unit of the first memory, on the basis of which a carry is effected to a next higher order position of the first memory. The first and second memories are address designated by a frequency division signal from a clock signal generator. The time count data in the address position of the first memory are compared at a comparator with the carry requirement numerical data in the corresponding address position of the second memory. When a coincidence signal emerges from the comparator the compared time count data of the address position of the first memory are cleared and "+1" is added to the next higher order address position of the first memory. When no coincidence signal appears from the comparator, counting is repeated at that address position of the first memory. The time count data are also displayed at an indicator. The timepiece does not require a conventional time count circuit as a time count means.</p> |
