发明名称 |
RANGE COUNT AND MAIN MEMORY ADDRESS ACCOUNTING SYSTEM |
摘要 |
In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control. |
申请公布号 |
AU3832578(A) |
申请公布日期 |
1980.01.31 |
申请号 |
AU19780038325 |
申请日期 |
1978.07.25 |
申请人 |
HONEYWELL INFORMATION SYSTEMS INC. |
发明人 |
EDWARD F. GETSON JR.;DONALD J. RATHBUN;JOHN H. KELLEY;ALBERT T. MCLAUGHLIN |
分类号 |
G06F5/10;G06F5/14;G06F13/12;G06F13/28 |
主分类号 |
G06F5/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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