PRODUCTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM

摘要

PURPOSE:To improve a carrier input efficiency and make a device small by designing the emitter of a npn transistor as a buring layer and a vertical structure and its base width controllable with a diffusing depth. CONSTITUTION:A P-buring layer 3 is formed selectively at a n<+> type Si basic board 1 to accumulate a n<-> epi layer 4 and produce a P-output layer 3'. A P layer 5 is produced with a SiO2 as a mask and a n<+> layer 6 is formed in the P layer 5 by striking a P ion into a SiO22' opened selectively. Then a grounded terminal Em is established at the basic board 1 to attach electrodes B, C1-C2 to its surface. This design accomplishes I<2>L system of both an inverter by the emitter 1 and a base 5 collector 6 and an injecter by the emitter 3, emitter 4 and collector 5. This structure ensures an ability of high speed movement to increase an efficiency of a carrier input. The fact that the emitter 1 of the injector is placed opposite to the collector 6 of the inventer decreases an ineffectual carrier and minimizes an ineffectual electric power.