发明名称 |
BUS CONTROL UNIT OF COMMON INPUT AND OUTPUT |
摘要 |
PURPOSE:To increase the overall efficiency of computer system by performing resetting with hardware without the aid of program, through the selective reset for the I/O in the common input and output bus reserved by CPU. CONSTITUTION:The reset signal emitted from CPU on P-BUS is delivered to I/O-BUS in the path of P-BUS wind switch on P-BUS wind switch on I/O-BUS. The reset signal is delivered to the I/O-BUS controller BC through the bidirectional reset line 10 provided every slot of I/O-BUS. BC receives this signal, and searches the CE on I/O-BUS used or reserved by CPU connected to the wind switch from the slot number mounting the wind switch through which the reset signal passes. |
申请公布号 |
JPS559248(A) |
申请公布日期 |
1980.01.23 |
申请号 |
JP19780081010 |
申请日期 |
1978.07.05 |
申请人 |
HITACHI LTD |
发明人 |
MORIOKA TAKAYUKI;IDE TOSHIYUKI |
分类号 |
G06F13/36;G06F3/00;G06F15/16;G06F15/177 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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