| 摘要 |
A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or "borderless") contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region. Elimination of contact borders advantageously reduces the overall area required for the contact, and consequently, reduces the overall surface area of the integrated circuit chip. Additionally, the metal step coverage at the contact edges is improved over prior art etched contact vias. The self-aligned contact via is achieved by repeated patterning of an oxidation barrier coupled with the intermediate step of thermally growing a thick insulation oxide layer over areas wherein devices such as FET's or bipolar transistors will be formed.
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