发明名称 FAULT GENERATOR FOR DATA PROCESSING SYSTEM
摘要 PURPOSE:To ensure the fault generation for an optional time to an optional device connected to the fault generator via the control of the CPU by providing the circuit which is controlled by the input/output control order of the CPU plus the fault setting circuit which sets the input/output state of the electronic circuit module. CONSTITUTION:Fault generator FGU is constituted by providing control circuit CTL which is controlled by the input/output control order of the CPU within data process system SYS plus fault setting circuit SW which sets the input/output state of electronic module PKG within optional unit UNIT within SYS. And the state can be controlled for an optional terminal of connection terminals T1-Tl of module PKG by the control orders of input/output cotnrol lines C1-Cm of the CPU, thus ensuring the fault generation for an optional time.
申请公布号 JPS54146554(A) 申请公布日期 1979.11.15
申请号 JP19780055199 申请日期 1978.05.09
申请人 NIPPON ELECTRIC CO 发明人 MINEMURA KIYOSHI
分类号 G06F11/22;G06F11/00 主分类号 G06F11/22
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