| 发明名称 |
MTJ structure and integration scheme |
| 摘要 |
A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. |
| 申请公布号 |
US9373782(B2) |
申请公布日期 |
2016.06.21 |
| 申请号 |
US201414518459 |
申请日期 |
2014.10.20 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
Li Xia;Kang Seung Hyuk;Nowak Matthew Michael |
| 分类号 |
H01L43/12;H01L43/08;H01L27/22 |
主分类号 |
H01L43/12 |
| 代理机构 |
|
代理人 |
Lo Elaine H. |
| 主权项 |
1. A method for fabricating a memory device, comprising:
depositing an MTJ stack including a free layer, a barrier layer, and a pinned layer, depositing a BE layer coupled to the MTJ stack, encapsulated in a planarized layer, and having a substantially common axis with the MTJ stack; and depositing a contact layer embedded in the BE layer, the contact layer forming an interface between the BE layer and the MTJ stack, wherein the contact layer is a first anti-ferromagnetic (AFM) layer and wherein the MTJ stack further includes a second AFM layer coupling the MTJ stack to the first AFM layer. |
| 地址 |
San Diego CA US |
