发明名称 Method of forming a plurality of P-N junctions spaced out in a monocrystalline silicon chip
摘要 A monocrystalline Si chip (25) of N type is provided with a SiO2 mask (26), pierced by a window (27), then is placed in a closed diffusion furnace containing pure gallium and gallium arsenide. After the diffusion processing, the chip contains an N-type core (31), a P- type envelope (30) formed by diffusion of the gallium through the mask and an N-type region (32) formed by diffusion of the arsenic through the window (27). Next, the mask (26) is dissolved and the chip is placed in an open diffusion furnace and is exposed to water vapour, which forms a new SiO2 coating over the whole surface and accentuates the differentiation of the P and N regions. Next, the window (27) is reformed and successive layers of Ni and Au are deposited thereon. Finally, the chip is abraded to expose the P and N regions. The device thus obtained is used as a thyristor. <IMAGE>
申请公布号 CH613562(A5) 申请公布日期 1979.09.28
申请号 CH19750011853 申请日期 1975.09.12
申请人 INTERNATIONAL RECTIFIER CORP. 发明人 GARY I. ROBERTS
分类号 H01L21/223;H01L21/225;H01L21/332;(IPC1-7):H01L21/22;H01L29/74 主分类号 H01L21/223
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