发明名称 INSULATING GATE FIELD EFFECT TRANSISTOR
摘要 PURPOSE:To raise the avalanche destruction voltage of the PN junction, which is formed by a drain region and a substrate, and enlarge the punch through voltage between the drain and the source by constituting the drain region by a high-impurity density region and a low-impurity density region sorrouding the region above. CONSTITUTION:On one conductive type semiconductor substrate 11 of the maximum impurity density of 10<4> to 10<6> atoms/cm<3>, opposite conductive type low- density drain region 19 of the maximum impurity density of 10<15> to 10<17> atoms/cm<3> and opposite conductive type high-density source region 13 of the maximum impurity of 10<18> to 10<21> atoms/cm<3> are formed by diffusion. Next, internal drain region 14 which has the same conductive type as substrate 11 and the maximum impurity density of 10<18> to 10<21> atoms/cm<3> and channel stopper 12 which has the same conductive type and density as region 14 are formed in region 19 by diffusion. After that, all the surface is covered with SiO2 film 15, and a window is provided. Then, source and drain electrodes 16 and 18 are fitted, and gate electrode 17 is caused to adhere onto film 15 between regions 13 and 14.
申请公布号 JPS54124688(A) 申请公布日期 1979.09.27
申请号 JP19780032701 申请日期 1978.03.20
申请人 NIPPON ELECTRIC CO 发明人 NAKAGAWARA AKIRA;ENDOU NOBUHIRO
分类号 H01L29/06;H01L29/78 主分类号 H01L29/06
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