| 摘要 |
PURPOSE:To enable to limit the flowing of positive power supply current, by restricting the application of the clock synchronizing signal to the board with the clock input control circuit through the reception of the output when the interruption of bias to the board is detected. CONSTITUTION:The integrated circuit 1 including the clock synchronizing N channel MOS circuit is provided with the terminal 2 to which a positive power supply is fed and the terminal 3 to which negative board bias is fed. The clock signal to the circuit 1 is fed to the terminal 4, and the clock input control circuit 6 is controlled with the output of the board bias interruption detection circuit 5. If the bias potential to the board bias terminal 3 is in failure such as interruption, the circuit 5 detects this and controls the circuit 6 so that the clock signal to the circuit 1 is inhibited or the intensity is reduced. Thus, the flowing of the positive power supply current can be limited. |
