发明名称 SPEED VARIABLEETYPE CENTRAL PROCESSING UNIT
摘要 <p>PURPOSE:To improve the processing efficiency of jobs by causing an instruction register or instruction decoder to receive instructions from a program and send signals to a frequency divider circuit to change the frequency division rate of clocks. CONSTITUTION:On one chip, clocks from clock oscillator 1 are frequency-divided by N variable 1/N frequency divider circuit 2, and clocks from circuit 2 are generated in polyphase by polyphase clock generator 3. Here, instruction register 4 and instruction decoder 5 receive instructions from a program and send them to circuit 2 to change the frequency division rate of clocks. As a result, the processing efficiency of jobs can be improved.</p>
申请公布号 JPS54117649(A) 申请公布日期 1979.09.12
申请号 JP19780025105 申请日期 1978.03.06
申请人 FUJITSU LTD 发明人 WADA KENSAKU;FUJITA KOUICHI;KIMURA MASAHARU;KOMINAI MASASHI
分类号 G06F9/30;G06F1/04;G06F1/08;G06F9/06 主分类号 G06F9/30
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