| 摘要 |
PURPOSE:To establish the comparison detection circuit which can not cause malfunction from the effect of the stray capacitance of the signal lines through which the counter output of the counter circut is delivered. CONSTITUTION:The signals q1 to q3 before a half bit shift for the counter output signals Q1 to Q3 of counter circuit 21 counting sequentially the clock pulse phi supplied and the bit data LD1 to LD3 preset are compared 44 each other. Further, this comparison signal is shifted 48 in a half bit of the clock pulse phi, so that the ''1'' level signal of the pulse length less than a half bit of the clock pulse phi established in the comparison signal can not be detected. Thus, the coincidence signal is established only when the number of count is in agreement with the number of counts expressed in the bit data LD1 to LD3 preset, therefore no malfunction can not be caused independently of the value of stray capacitance of the delivery signal lines. |
